PLE - physical layout estimator

Hi Mattan,

For you question (1), I think there is a swift in mindset in pre-layout synthesis not to care about net length. I am not R&D, but if you understand gain-base methodology (I think gain-base is public domain, and not patented. Anyone can correct me here?) The following is a short explanation on how this can be done:

1. From the .lib, we can calculate the delay of a cell if it is in an "average critical path" (e.g. the output load is 2.7 times of input cap. Sometime refer to ideal load, as it is related to the fastest way to drive a large load)
2. Using design constraint (e.g. SDC) and using the delay in (1), we can find out the paths that fail and paths that pass.
3. For paths that failed, we can make the cell faster (in layout term, it mean very short wire, and less fan-out), but there is a limit how fast the cell can be made faster, and how many cell can be made faster (in layout term, we can put some cells very close together, but we cannot put many cells close together). Those cells with delay shorter than (1) and is in the path with negative slack not now in "super critical path".
4. For paths that pass, we can make the cell slower by using slower architecture and lower drive strenght.

RC might use a totally different approach, but I just wish to point out that with this type of "timing budget process", you ready can don't care about the wireload/wire-length (see step 1-4 above that no wireload estimation is made).

By the way, I was told that even the application engineers have very little knowledge about LPE, so I think this wondering LPE method is kept a tight secret!

Regards,
Eng Han

Hi Mattan,

For you question (1), I think there is a swift in mindset in pre-layout synthesis not to care about net length. I am not R&D, but if you understand gain-base methodology (I think gain-base is public domain, and not patented. Anyone can correct me here?) The following is a short explanation on how this can be done:

1. From the .lib, we can calculate the delay of a cell if it is in an "average critical path" (e.g. the output load is 2.7 times of input cap. Sometime refer to ideal load, as it is related to the fastest way to drive a large load)
2. Using design constraint (e.g. SDC) and using the delay in (1), we can find out the paths that fail and paths that pass.
3. For paths that failed, we can make the cell faster (in layout term, it mean very short wire, and less fan-out), but there is a limit how fast the cell can be made faster, and how many cell can be made faster (in layout term, we can put some cells very close together, but we cannot put many cells close together). Those cells with delay shorter than (1) and is in the path with negative slack not now in "super critical path".
4. For paths that pass, we can make the cell slower by using slower architecture and lower drive strenght.

RC might use a totally different approach, but I just wish to point out that with this type of "timing budget process", you ready can don't care about the wireload/wire-length (see step 1-4 above that no wireload estimation is made).

By the way, I was told that even the application engineers have very little knowledge about LPE, so I think this wondering LPE method is kept a tight secret!

Regards,
Eng Han