RC compiler issue with vlog2001

Hi
A verilog source file has the following code for inferring a flop with asynchronous reset on posedge
always @ (posedge clk or posedge rst)
  q[SIZE-1:0] 
 
The above is valid vlog2001 syntax. Unfortunately the RTL compiler is erroring out with the following message.

Error   : An 'if' statement is required at the top of an always block to infer a latch or flip-flop. [VLOGPT-46] [_read_hdl]
        : in file 'swrvr_clib.v' on line 419, column 3.
        : The supported syntax for asynchronous set-reset on a flop-flop is:
    reg data_out;
    always @(posedge clock or posedge reset)
        if ( reset )
            data_out = 1'b1;
        else
            data_out = 1'b0.

Does RTLC not infer flops in case of vlog2001? Changing the source code is not an option.
I was wondering if a user-option had been left out in the config file.

Appreciate any help in this matter
-Sudeep