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PLE adjusting in Rtl compiler

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Hi guys,

Does anybody know how to adjust PLE setting in RTL compiler so it will be more in line with encounter results?

I heard somebody talk about it, but he is not available now.

Any help would be appreciated.

Thanks,

Manzur.


Originally posted in cdnusers.org by myazdani
Parents

  • GH, it is really great!

    Besides that, below is what Cadence support says about correlating PLE results during STA.

    Cristiano.

    #####
    Cristiano.
    RC has the 'write_set_load' command. This command will write out a file
    which includes a set_load for every net in the design. The user can then load
    the netlist and SDCs into the timing tool, followed by this set_load file.
    This *should* enable the timing tool to 'see' the same timing as RC PLE. That
    is, it uses the same wire delays as RC in PLE mode. RC will not tell how PLE
    does it, but it provides the value that PLE picked.
    #####


    Originally posted in cdnusers.org by clsantos
Reply

  • GH, it is really great!

    Besides that, below is what Cadence support says about correlating PLE results during STA.

    Cristiano.

    #####
    Cristiano.
    RC has the 'write_set_load' command. This command will write out a file
    which includes a set_load for every net in the design. The user can then load
    the netlist and SDCs into the timing tool, followed by this set_load file.
    This *should* enable the timing tool to 'see' the same timing as RC PLE. That
    is, it uses the same wire delays as RC in PLE mode. RC will not tell how PLE
    does it, but it provides the value that PLE picked.
    #####


    Originally posted in cdnusers.org by clsantos
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