using RTL Compiler as Static Timing Analysis

Hi,
The command "report timing -lint -verbose" will give you all unconstrained input and outputs.

Thank you very much for the kind info.

Additional question regarding this issue:

Maybe it will be ridiculuous to ask, but does setting cost groups/path groups in the flow stated in the first posting of this thread (ie. setup lib, read netlist, read SDC, gen reports) have effect on the timing results?

Does the timing analyzer engine in RC take cost/path groups into account?

I put my question other words:

when I use RC as an STA Tool, does the change of cost/path groups in a design have an effect on timing analysis calculations? For ex:
1. setup lib, read netlist, read SDC
2. define a cost/path group setting
3. report_timing
4. change cost/path groups
5. report_timing

Can the timing analyzer inside RC called by report_timing generate different results? Does any change on cost/path groups change the behavior of analysis?

Please note that I DON'T USE RC for synthesis but for [b]static timing analysis[/b].

Greetings Sporadic Crash, as far as I know, cost groups should have no effect on delay calculation. Cost groups serve two main purposes in my mind: + guide the optimization engine when a slow memory or part of the logic is affecting the targets for the whole design + for reporting purposes if you need to categorize based on some criteria good luck, G-

One of the thing that happen when you create path groups is that a path that used to be reported in a default group is not anymore so the path orders might be different but if you do a report_timing point to point it should still be the same before and after just the group might be different.