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Clock gating cells constraints

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Hello,

    I have multicycle paths from control registers to enable pin of clock gating cells.
In RTL - Compiler CG cells are added only during synth -to_map stage, after synth -to_gen there are no "unmapped" CG cells. This forces me to add multicycle paths to CG cells only after mapping.
It causes significally increased runtime, because during the mapping RC tries to close path to the enable of CG cell and work less on other pathes. The CG constraints are set after the mapping and incremental synthesis is used to close other paths, that still remain violated.
    Any suggestion how to set the constraints before mapping?

Thanks in advance.


Originally posted in cdnusers.org by Stalker

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