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CDC functional checks are not validated for design.

vaizguy

Hello everyone, I was recently required to perform both structural CDC checks and functional CDC checks on a design but when I go through the reports I noticed that the structural checks are performed fine but the functional reports simply say that the paths are not validated. I would like to know why these functional checks aren't being performed as there are no warnings in the log indicating why. Even the GUI has a question mark next to the functional checks tab. while the structural checks has a green/red dot next to it indicating pass/fail resp.

The tool is unable to detect direct bus synchronization instances like the following example and I was hoping that performing functional checks especially the single_bit_change check would highlight all such paths.

Eg.
input [3:0] A; // In clkA domain.
reg [3:0] B_r;
output reg [3:0] B_rr; // In clkB domain.

always @(posedge clkB) begin
  B_r <= A;
  B_rr <= B_r; // This is fine when A is a single bit.
end

Thanks in advance.

Parents
  •  Your dofile should look something like this:

    set log file cdc.log -replace                                      

    set flatten model -noncontrolling_remodel

    add search path rtl

    read design rtl/fsm.v s_d_data.v sync.v top.v

    set clock_domain rule -extract -noderived

    add pin constraint 1 rstan

    add pin constraint 1 rstbn

    add clock 0 -waveform 1 1 2 clka

    add clock 0 -waveform 3 3 6 clkb

    read initial state init.seq

    set system mode verify

    add sync rule dff -dff 2 -sync_chain buffer single_chain -cdc_path buffer single_destination

    add sync rule mux -mux 0 0 -hold -cdc_path buffer single_destination

    add cdc check -structural -source -all -destination -all -from -all -to -all

    validate

    add cdc check -functional -source -all -destination -all -from -all -to -all

    validate

     

    Is this what you basically have?

    Let me know.

    Regards,  Clay
Reply
  •  Your dofile should look something like this:

    set log file cdc.log -replace                                      

    set flatten model -noncontrolling_remodel

    add search path rtl

    read design rtl/fsm.v s_d_data.v sync.v top.v

    set clock_domain rule -extract -noderived

    add pin constraint 1 rstan

    add pin constraint 1 rstbn

    add clock 0 -waveform 1 1 2 clka

    add clock 0 -waveform 3 3 6 clkb

    read initial state init.seq

    set system mode verify

    add sync rule dff -dff 2 -sync_chain buffer single_chain -cdc_path buffer single_destination

    add sync rule mux -mux 0 0 -hold -cdc_path buffer single_destination

    add cdc check -structural -source -all -destination -all -from -all -to -all

    validate

    add cdc check -functional -source -all -destination -all -from -all -to -all

    validate

     

    Is this what you basically have?

    Let me know.

    Regards,  Clay
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