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RTL Compiler: 1'b0/1'b1 instead of LOGIC0/LOGIC1 cells

Hi,

RTL Complier is apparently unable to use target library cell called LOGIC0 and LOGIC1 to drive unused pins. I get something like this instead:

DFC3 \add_iter_reg[0] (.RN ( 1'b1 ), .C (clk), .D (n_18), .Q(adres[0]), .QN ());

Could somebody tell me what attribute should I set to prevent such behaviour?

Regards

Zbigniew Jaworski

Originally posted in cdnusers.org by zjaworski

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archive over 18 years ago

RC does not automatically insert tie cells. You need to use the script insert_tiehilo_cells.tcl in the /etc directory. include load_etc.tcl insert_tiehilo_cells

Originally posted in cdnusers.org by synthman
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archive over 18 years ago

RC does not automatically insert tie cells. You need to use the script insert_tiehilo_cells.tcl in the /etc directory. include load_etc.tcl insert_tiehilo_cells

Originally posted in cdnusers.org by synthman
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