I am synthesizing a top level digital block that has interfaces to external pads and to a top level analog block.
When I run DFT checks, it assumes that all ports are controllable, which is not the case for the signals from the top level analog block.
Is the an attribute I can apply to these ports to indicate that they are not controllable?
Having checked further, this is not what I want. This attribute only applies to pins, and is intended for internal black boxes.
I need something to apply to design ports, and to indicate that a pin is not controllable (even though it is a primary input)
Any additonal suggestions?