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RC synthesis flows

sureshm

 Dear all,

The question may be quite trivial for many out in this forum .. .i would like to discuss more of a methodology related  question with respect to RC tool usage ...for synthesis .!!! 

What are the several Synthesis flows recommended by RTL compiler? 

 Not all designs are computational intensive datapaths,  Few are intensive datapaths, Few are Clock intensive paths( more of clock path generation) and few designs  are  Memory intensive..  

 What is the best way to deal with each type of the Designs interms of methodologies .. ? how do we ensure that we have optimized the best possible way? How to verify for any improvements in the design QoR, timing, area & power...?

Apart from CG gating, what other techniques do we employee to target the low power synthesis?  

I also found that Multi-Vt optimization in synthesis is not a  good idea  from the tool perspective as this is not giving a good results?

Usually, DC provides a lot of template scripts targetting for timing, area & power separately? Any such tricks available in RTL compiler as well?? 

 Please share your views !! 

 

thanks

suresh 

Parents

  • Hi gh,

     When i am doing Zero WL for nets, I am not enabling the PLE Synthesis. Infact, we did couple of experiements with the block sizes and the nature of the clocks, finally came to an experimental number that worked with most of the designs/blocks  of our chip.  PLE with 5-10% of clock frequency is almost giving the similar results in QoR.  I wonder, if we get any additional advantage using PLE synthesis with  5-10% of  Clock Frequency as oppose to 20% (Zero WL).

     You are right, Nothing comes for free..!! In order to achieve something, it costs something else :) .I am mistaken in the previous message.

     Thanks

    suresh

     

     

Reply

  • Hi gh,

     When i am doing Zero WL for nets, I am not enabling the PLE Synthesis. Infact, we did couple of experiements with the block sizes and the nature of the clocks, finally came to an experimental number that worked with most of the designs/blocks  of our chip.  PLE with 5-10% of clock frequency is almost giving the similar results in QoR.  I wonder, if we get any additional advantage using PLE synthesis with  5-10% of  Clock Frequency as oppose to 20% (Zero WL).

     You are right, Nothing comes for free..!! In order to achieve something, it costs something else :) .I am mistaken in the previous message.

     Thanks

    suresh

     

     

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