Did you try 'analyze setup'/'set analyze option -auto'?
You have type 'Z' as an unmapped in the golden. By default that's how LEC treats undriven signals. DC would ground them. Are you using 'set undriven signal 0 -golden' so LEC matches DC?
Glad to read that your design is now EQ.
Please note that
'set undriven signal 0 -golden'
is a global constraint and can change the design behavior from RTL simulations. If the RTL has undriven signals, ideally they are fixed in the RTL to be driven. If that is not possible, it is safer to drive specific signals rather than globally forcing them.
If driving unconnected signals is temporarily needed for an unfinished design then echo statements in the dofile can help warning the user that temporary constraints have been added.
There is a nice Solution article on this
It makes for an interesting read.