1. Can someone please explain what is the exact meaning of clock latency.
2. What is the meaning of the following RC scripts
1. path_adjust -from clk2 -name latency1 -delay -30
2. path_adjust -to clk2 -name latency2 -delay 30
where :- one pin named "clk2" is the internal clock source pin of the PLL and the other clk2 is the clock port of some block.
why is the latency specified in terms of negative time (-30ps). ?