RTL Compiler - read_tcf - Cannot read TCF file when using Generate verilog statement

Hi

Here I am describing an issue that I have seen using RC 10.1 and NCSim 9. 

In order to estimate power with RC we need to read circuit switching activity as TCF/VCD files.

As of my tests the VCD reader engine of RC 10.1 has bugs. So, i don't use it at all. 

For reading TCF file, 

if I use "generate" verilog statement, for instantiating a module several time, then when I simulate the design and create TCF file, then when I try to read the TCF inside RC , i will see this message and read_tcf stops working. 

"unmatched open brace in list"

so actually, the tool can not read the TCF file produced by NCSim. 

on the NCSim side the simulation is fine and it goes until end with no problem. 

Now, if I remove the "generate" verilog statement and i do instantiation manually,

every thing works fine.