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How to synthesize without scan cell replacement

Maso

Hi,

 I synthesize RTL with RTL Compiler.

I have setup below options.

set_attr dft_connect_scan_data_pins_during_mapping ground [find / -design *]
set_attr dft_connect_shift_enable_during_mapping tie_off [find / -design *]
set_attr dft_scan_map_mode preserve [find / -design *]

But when I finished synthesis, I always get my netlist with scan cells replacement.

How can I avoid the scan cells replacement ?

 Thanks a lot.

Parents

  •  Sorry for the delayed reply.

    The attributes you initially posted should tie off both the SE and SI pins:
       set_attr dft_connect_scan_data_pins_during_mapping ground [find / -design *]
       set_attr dft_connect_shift_enable_during_mapping tie_off [find / -design *]

     Keep in mind that grounding the SI pin eliminates some of the benefit of inserting scan flops during mapping.  Usually you want to loop back the Q pin to the SI pin so that an extra load is seen on the Q pin.  This prevents timing from changing after connecting the scan chains.

    I suspect RC mapped to the above flop because it is using the scan mux for "functional" purposes, not scan purposes.  Using the attribute I mentioned in my last email should prevent that:

          set_attr use_scan_seqs_for_non_dft false /

    However, what you really need to determine is why LEC is failing.  If the RC netlist matches the RTL (or post-map netlist), then you can safely assume it is correct.  Be sure scan_enable is constrained in the post-DFT-Compiler netlist (revised netlist in LEC).  You shouldn't see any noneqs unless something went wrong while the scan chains were built.

    Good luck!

    Brad

     

Reply

  •  Sorry for the delayed reply.

    The attributes you initially posted should tie off both the SE and SI pins:
       set_attr dft_connect_scan_data_pins_during_mapping ground [find / -design *]
       set_attr dft_connect_shift_enable_during_mapping tie_off [find / -design *]

     Keep in mind that grounding the SI pin eliminates some of the benefit of inserting scan flops during mapping.  Usually you want to loop back the Q pin to the SI pin so that an extra load is seen on the Q pin.  This prevents timing from changing after connecting the scan chains.

    I suspect RC mapped to the above flop because it is using the scan mux for "functional" purposes, not scan purposes.  Using the attribute I mentioned in my last email should prevent that:

          set_attr use_scan_seqs_for_non_dft false /

    However, what you really need to determine is why LEC is failing.  If the RC netlist matches the RTL (or post-map netlist), then you can safely assume it is correct.  Be sure scan_enable is constrained in the post-DFT-Compiler netlist (revised netlist in LEC).  You shouldn't see any noneqs unless something went wrong while the scan chains were built.

    Good luck!

    Brad

     

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