I synthesize RTL with RTL Compiler.
I have setup below options.
set_attr dft_connect_scan_data_pins_during_mapping ground [find / -design *]set_attr dft_connect_shift_enable_during_mapping tie_off [find / -design *]set_attr dft_scan_map_mode preserve [find / -design *]
But when I finished synthesis, I always get my netlist with scan cells replacement.
How can I avoid the scan cells replacement ?
Thanks a lot.
RC can produce a dofile for a variety of tools including LEC. The command is write_do_lec. If you are not using this command then you can try that.
If RC has the DFT signals correctly defined then the generated write_do_lec dofile will add the needed LEC DFT constraints. If the RC has some question on the constraints (maybe not safe) then the constraints will still be there but commented out. You can then review them and uncomment them.
One can also manually constrain nets and instances in LEC. To constrain a net you can do this:
add primary input top/testpin/q -bothadd pin constraint 0 top/testpin/q -both
Plus there is also "add instance constraint" for flops/latches.