I synthesize RTL with RTL Compiler.
I have setup below options.
set_attr dft_connect_scan_data_pins_during_mapping ground [find / -design *]set_attr dft_connect_shift_enable_during_mapping tie_off [find / -design *]set_attr dft_scan_map_mode preserve [find / -design *]
But when I finished synthesis, I always get my netlist with scan cells replacement.
How can I avoid the scan cells replacement ?
Thanks a lot.
I am not sure I understand. Conformal LEC fails between what two netlists? RTL vs gates? Are you using the recommended two-step verification flow; RTL vs mapped-gates, and mapped-gates vs final-gates?
I originally understood that you had an LEC noneq between the RC synthesised gates and the DC DFT-Inserted gates.
From what you describe, it is possible that LEC is having trouble understanding an RC sequential constant optimization. Try adding "-effort high" to "set analyze option -auto" in the dofile.
If that doesn't work, file a 'service request" (SR) on support.cadence.com. The Conformal Customer Support engineers are very good.
No, RC cannot write an SVF file. It is a proprietary format.