I synthesize RTL with RTL Compiler.
I have setup below options.
set_attr dft_connect_scan_data_pins_during_mapping ground [find / -design *]set_attr dft_connect_shift_enable_during_mapping tie_off [find / -design *]set_attr dft_scan_map_mode preserve [find / -design *]
But when I finished synthesis, I always get my netlist with scan cells replacement.
How can I avoid the scan cells replacement ?
Thanks a lot.
Sorry for mixing two case.
The original case -
I set below option to do synthesis:
set_attribute optimize_constant_0_flops false /set_attribute optimize_constant_1_flops false /
LEC can pass.
And then I use DC DFT to insert scan chain.
Formality fail for synthesis netlist and dft netlist.
As mentioned in last mail, it's work to avoid scan cell replacement by using "set_attr use_scan_seqs_for_non_dft false /".
I have re-run formality to check the result, and it can pass.
Another case -
I set optimize_constant to true.
In this case, I have tried -effor high but it's no use.
I will file a 'service reqest' on support.cadence.com later.
You help me a lot.
Thanks for your help very much.