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Can't simulate with gate delays.

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Hi, I'm new in hardware designs and cadence tools, and I read allot of texts but I'm still with a doubt:

How can I simulate my design after synthesis with gates delay!?

I'm doing these comands in RC Compiler to synthesize:

set_attribute library /eda/xfab/xh035/cadence/xh035/D_CELLS.lib
read_hdl time_base_timer.v
read_hdl edgedetect.v
elaborate define_clock -period 125000 -name fc_clk_i
synthesize -to_mapped
write_sdf > done_tbt_delay.sdf

After that I'm using nclaunch to simulate, and doesn't matter if I use or not the sdf file every single gate stay with a delay of 100ns.

Anyone know something about it? I didn't find nothing about it in this forum...

Thanks!

PS: I'm using the xfab lib.



Originally posted in cdnusers.org by JoeArny

  • JoeArny,

    this, most likely has little to do with RTL Compiler an more to do with your simulation setup. Make sure you have simulation models for the cells and that you have setup all your compiler directives appropriately. `UNIT_DELAY is one commonly used to switch gate delays between a generic number and the one coming from the annotation. Also verify that the SDF got annotated without erroring when you read it in. For additional details on the simulation setup I would post on the simulation forum if there is one.

    good luck,
    gh-


    Originally posted in cdnusers.org by grasshopper

  • Hi grasshopper, thanks about your reply..

    I'll read more about the nclaunch and go to simulation forum, as you said. :)

    About UNIT_DELAY, thanks about the Tip...!!! ;)

    []'s


    Originally posted in cdnusers.org by JoeArny

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