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Checking equivalence of buffer trees

BufferTree

Hello,

I have two netlists, a revised and a golden, both containing a mesh/tree hybrid comprised entirely of inverters. There are multi-driven nets and bidirectional ports galore, but the input to the tree is a pin/net called "clk", and the output is a net called "GCK".

When I load these two netlists into Conformal, I get this message when attempting to run a compare:

 LEC> compare
// Command: compare
// Nothing to compare. 'Add compared points' first.

 When attempting to add a compare point, I get:

 LEC> add compared points clk -golden
// Command: add compared points clk -golden
These mapped points are not compared:
  (G) + 1   PI   /clk
  (R) + 1   PI   /clk

LEC> add compared points clk -revised
// Command: add compared points clk -revised
// Warning: 'clk' in Revised is not a mapped point
// Warning: No compared point is added

When attempting to add a mapped point, I see:
 
 LEC> add compared points clk -golden
// Command: add compared points clk -golden
These mapped points are not compared:
  (G) + 1   PI   /clk
  (R) + 1   PI   /clk
LEC> add compared points clk -revised
// Command: add compared points clk -revised
// Warning: 'clk' in Revised is not a mapped point
// Warning: No compared point is added
 
Is there a guide to comparing netlists without sequential elements?
If not, could someone walk me through the basics of comparing netlists without sequential elements, and the creation of compare points?
 
I'm more than happy to go read up on this, but the  "Mapping Modifications" section of the User Guide wasn't helping me.
 
Thanks in advance!
~BufferTree 

  • Hi.

    A very basic example dofile is as follows. You may not need some of the options but this is a good start for much designs.


    read library -verilog -replace -both <lib_files>

    read design -verilog -golden <design_files>

    read design -verilog -revised <design_netlist>

    report design data

    report black box -detail

    add pin constraint 0 scan_en  -golden/revised

    add ignore output  scan_out -golden/revised

    set flatten model  -seq_constant

    set flatten model  -gated_clock

    set analyze option -auto

    set parallel option -threads 4

    set system mode lec

    add compared point -all

    compare

     

    It seems like your main problem is with "add compared points". You are only trying to compare the input clk in your design. This isn't adding the needed compare points to your design.

    There is this new Web Interface feature (11.1) that for me has a lot of good information. You may try that or the LEC Jumpstart which is a good starting point.

    > set web on

    http://tinyurl.com/cadence-rak   (look for jumpstart).

     

    -stark

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