typedef enum in SV

Hi there,

I ve written a module by using typedef enum as shown below and it cannot be synthesis. Syntax Error stated :
- Expecting module level statement
- Expecting target variable, got p_state - Misspelling?
- Expecting radix character (one of b, o, h, or d) or unsized single bit literal (one of '1, '0, 'x, 'z)

Can anyone give me some advice on this? thank you very much.

typedef enum logic ?:0]{
 Idle = 0,
 Fetch = 1,
 Exe = 2
} state_type;
state_type p_state, n_state;

always @ ( posedge clk or negedge nreset)
begin
  if (~nreset)
    p_state = state_type'(Idle);
  else if (clk)
    p_state = n_state;
end