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Simulating verilog using cadence

Hi!

I am new to this forum so please bear with me if my question is basic, anyways here goes. I am trying to simulate a state machine (kind of) in cadence using the ams simulator. NOw I have tested and verified that the design works using model sim. When I try to simulate it using the ams simulator the output appears to x (or connected I assume). Can anyone please guide me what I am doing wrong.

MTP3 over 13 years ago

So I figured it out the Dffs had to be reset intially for the circuit to operate I didn't occur to me first as I was treating it as an analog simulation but restting it does the trick.
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