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setting rc constraints

Hello designers,

I would like to simulate a variable ring oscillator with .sdf, but the rtl compiler is optimizing the design during the elaboration step impeding me to simulate it later on with .sdf.
Is there a way to preserve my module so that the rtl compiler will not optimize my series of inverters?

Thank you,

Originally posted in cdnusers.org by alexsieh

archive over 17 years ago

Hi alexsieh,

sounds like you want to use the preserve attribute. Try

> get_attr -h preserve *

for detailed information

gh-

Originally posted in cdnusers.org by grasshopper
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