Hi, I have now seen this issue with two different designs and have not been able to figure out the root cause for this behaviour.
I have synthesized a design using RTL Compiler and have generated both mapped and an optimized netlist.
1. When I compare the RTL to mapped netlist (non-hierarchical comparison), I don't see any non-equivalent points.
2. When I compare the mapped netlist to the final optimized netlist, I don't see any non-equivalent points.
3. But when I compare RTL to final optimized netlist, I get non-equivalent points.
Looking into this matter in detail, I noticed that these non-equivalent points start showing up as soon as I run the first incremental synthesis on the mapped netlist.
Any ideas as to why the RTL to final netlist comparison are showing non-equivalencies?
I have seen this happen before too, and in my case it was caused by sequential merging in RTL-Compiler. The two step LEC flow helps LEC resolve and verify sequential merging. The single step verification flow can often resolve sequential merging, but sometimes it cannot.
The two step LEC flow is the recommended way to verify RC netlists. I suggest you continue to use the two step flow. It is the best way to prevent false-noneqs and aborts.