Hi, I have now seen this issue with two different designs and have not been able to figure out the root cause for this behaviour.
I have synthesized a design using RTL Compiler and have generated both mapped and an optimized netlist.
1. When I compare the RTL to mapped netlist (non-hierarchical comparison), I don't see any non-equivalent points.
2. When I compare the mapped netlist to the final optimized netlist, I don't see any non-equivalent points.
3. But when I compare RTL to final optimized netlist, I get non-equivalent points.
Looking into this matter in detail, I noticed that these non-equivalent points start showing up as soon as I run the first incremental synthesis on the mapped netlist.
Any ideas as to why the RTL to final netlist comparison are showing non-equivalencies?
You can certainly rely on the final result whether you run flat or hierarchical.
If you'd like to have the option to run both ways, I suggest writing out two LEC dofiles with the write_do_lec command; one with -flat, and one without.
But, the preferred method is to run hierarchical if RTL is golden.