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how to add synthesizable delay in design

yasir khan over 13 years ago

I am trying to add a delay of 3ns and 5 ns in my design but it not synthesizable in RC-compilor..

anyone have idea how to add a synthesizable deslay in verilog.....

thanks

Paul Bibin over 12 years ago

At RTL stage you can add delays either by registers /counter
However during backend phase delays can be incorporated by adding buffers /delay elements in the design.
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