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I have a few questions regarding using Encounter RTL compiler. First, is RTL compiler an equivalent of the Synopsys Desing Complier tool? Both Synthesize the RTL verilog code to a gate-level netlist? Second, as an user in academic institutions, we have downloaded technology packages from MOSIS and the one we are currently using ARM/Artisan library for IBM 0.13um technology. However, I am having trouble with RTL compiler with this library? Should I set "lib_search_path" to the directory where the standard cells are located? Also, I could not find a .lbr or .lib file from the ARM/Artisan library, so I do not know how to set "library"? Do I have to create that file myself? Does anyone have used MOSIS ARM/Artisan before? Your help is highly appreciated.


Originally posted in cdnusers.org by cdnhua

  • Hi Friend,
    RC is simillar to DC from SNPS. Please use write_template command in RC to generate an template rc script and read the user guide document for more information about commands.

    Thanks
    Aravind R


    Originally posted in cdnusers.org by aravindhere

  •  The .lib describe timing, power and funtionnality of standard cells, it's a mandatory file for synthesis. ARM give it, you can't generate it (although you want to characterize all cells :-))...

     

    In unix shell type this find . -name "*.lib" , if you have no result, call ARM.

    ConcerningRTL compiler, you have to set library path, and hdl path before, you can find it in cadence documentation (preparing the design section, i think).

     

     

  •  If you have the same hierarchy for files, you can find your .lib here

     

    <main_directory>/<techno_name>/synthesis/<techno_name>/aci/sc-m/synospsys/

     There are .lib, and .db (compiled .lib, i.e. binary file of .lib)

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