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LEC and Designware components

Any method to resolve a blackboxed designware component on RTL netlist which does not match up to GATE level netlist?

Due to scan insertion on the DW_ram* module in gate leve netlist, LEC will not allow me to match up blackboxes between the golden and revised netlists.

Any help on this one? I can see if I have a sythesizable model in RTL this would likely work, but even the DW_ram* provided by LEC is not sythesizable.

affaqq over 13 years ago

I am on vacations so might not be able to respond timely. I will get back to work from 2nd Sept, 2012.

Ciao!

Affaq Qamar
Mob:+3280294862
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