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How to Simulate 64-bit VHDL Code in Cadence?

I am trying to simulate a VHDL code which have internally values exceeds the range of (-2**31 to 2**31). However, I can synthesize the code but I can't simulate it.

I tried to change the attribute

set intovf_severity_level IGNORE

but it didn't work as well.

I would appreciate your suggestions.

Regards.

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