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  3. -binding flag is ignored by ncelab

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-binding flag is ignored by ncelab

myonlyscreen
myonlyscreen over 12 years ago

Hi all

I am using IUS 11.1 and having problem with the -binding flag at the ncelab.

The ncelab ignores this flag and issues the next warning:

ncelab: *W,BINDIG: -binding ignored for verilog units.

In the past and in old versions i didn't have any problem binding verilog modules with this flag.

I will happy to hear from someone who faced this problem or know how to solve it.

Regards.

Eyal.

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  • TAM1
    TAM1 over 12 years ago

    The extended help for that message says:

    % nchelp ncelab BINDIG
    nchelp: 09.20-s055: (c) Copyright 1995-2012 Cadence Design Systems, Inc.
    ncelab/BINDIG =
            The elaborator has been invoked with the -XLMODE flag. It is assumed
            that the -XLMODE option builds a list for all verilog bindings at the
            parse time. This option will not override any of the bindings set in
            place by the parser.

    If you share your command line we might be able to figure out why the elaborator is being passed the -xlmode flag.

     

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  • myonlyscreen
    myonlyscreen over 12 years ago

    Hi TAM1

    Thanks for the quick response.

    I am familiar with the extended help message you posted, it was also been suggested by the Ncbrowse tool.

    I am not using the -XLMODE flag in my irun command and as far as I know it is invoked within the Ncelab internally.

    I attaching my irun log to this post , tell me if it tells you something that I am missing (sorry for the length of it).

    Regards.

    Eyal.

    ----------------------------------------------------------------------------------------------------------------------

    irun(64): 11.10-s053: (c) Copyright 1995-2012 Cadence Design Systems, Inc.
    TOOL:    irun(64)    11.10-s053: Started on Oct 04, 2012 at 17:11:12 IST
    irun
        -c
        /vobs/wlip_zebra/verif/wl_phy/SPECMAN/E_USR/precompile.e
        -nowarn DLCPTH:DLNCML
        /vobs/wlip_zebra/verif/wl_phy/SPECMAN/HDL/wl_phy_tb.v
        -nclibdirname SNAPSHOTS/wl_phy_tb
        -CDS_IMPLICIT_TMPDir SNAPSHOTS/wl_phy_tb
        -snvlog
        -sntimescale 1ps
        -snshlib /vobs/wlip_zebra/verif/wl_phy/SPECMAN/objects/libsn_ies_specman_exe.so
        -binding current.bl_CortexM3Integration:empty
        -relax
        -TIMESCALE 1ps/1ps
        -cdslib /vobs/wlip_zebra/ti_directives/cds.lib
        -access rwc
        -loadpli1 debpli.so:novas_pli_boot
        -nowarn DLCPTH:DLNCML:CUSRCH:CUDEFB:CSINFI
        -ncerror CUNOTB
        -sncompargs -enable_DAC
        -sv
        -define USE_OVL
        -access rwc
        -loadpli1 AlgoShared.so:bootstrap
        -clean
        -snapshot wl_phy_tb
        -l /vobs/wlip_zebra/verif/wl_phy/SPECMAN/LOGS/irun_snapshot_wl_phy_tb.log
        -log_ncvhdl /vobs/wlip_zebra/verif/wl_phy/SPECMAN/LOGS/ncvhdl_wl_phy_tb.log
        -log_ncvlog /vobs/wlip_zebra/verif/wl_phy/SPECMAN/LOGS/ncvlog_wl_phy_tb.log
        -log_ncelab /vobs/wlip_zebra/verif/wl_phy/SPECMAN/LOGS/ncelab_wl_phy_tb.log
        -nowarn DLNCML

       The following environmental variables have been detected.
       These options will be used directly by the executables and ignored by irun.
        NCVLOGOPTS: -NOCOPYRIGHT -MESSAGES -NOWARN DLNCML -NOWARN DLCPTH -NOWARN WARIPR -assert -view rtl -define ABV_ON
        NCVHDLOPTS: -NOCOPYRIGHT -MESSAGES -NOWARN DLNCML -NOWARN DLCPTH -RELAX -V93
        NCELABOPTS: -NOCOPYRIGHT -MESSAGES -ACCESS +RWC -NOWARN DLNCML -NOWARN DLCPTH -RELAX -namemap_mixgen
        NCSIMOPTS: -MESSAGES -NOCOPYRIGHT -NOWARN DLNCML -NOWARN DLCPTH

    irun: *N,SNPREC: The existing contents of the environment SPECMAN_PRE_COMMANDS will only be passed on to the simulation phase (set_config(cover,dir,"/vobs/wlip_zebra/verif/wl_phy/SPECMAN/ECOV");set_config(memory,max_size,2000M,absolute_max_size,1900M,gc_threshold,500M,gc_increment,500M);set_config(run, tick_max, 1024M);set_config(cover,show_sub_holes,TRUE);set_config(cover,auto_cover_events,TRUE); set_config(cover,write_model,ucm);set_config(cover,database_format,ucd);).
    irun: *N,CLEAN: Removing existing directory SNAPSHOTS/wl_phy_tb.
    # sn_compile.sh: Reading Specman Elite init file - $SPECMAN_HOME/system.specman
    #------------------------------------------------------------
    # Welcome to sn_compile.sh (version: 11.10.050-s, 64 bit)
    # sn_compile.sh: executing with args:
    # sn_compile.sh -shlib -cflags -I../../../.. /vobs/wlip_zebra/verif/wl_phy/SPECMAN/E_USR/precompile.e -enable_DAC -e SNAPSHOTS/wl_phy_tb/wl_phy_tb.lnx8664.11.10.nc/specman.11.10.050-s/scratch -t SNAPSHOTS/wl_phy_tb/wl_phy_tb.lnx8664.11.10.nc/specman.11.10.050-s/scratch/precomp_tmp -o libsn_precomp.so -s /sim1/zebra/wl_phy/wlip_zebra_eyalm/SNAPSHOTS/wl_phy_tb/wl_phy_tb.lnx8664.11.10.nc/specman.11.10.050-s/scratch/wrap_libsn_ies_specman_exe.so
    #------------------------------------------------------------
    #------------------------------------------------------------
    # Translating  using /sim1/zebra/wl_phy/wlip_zebra_eyalm/SNAPSHOTS/wl_phy_tb/wl_phy_tb.lnx8664.11.10.nc/specman.11.10.050-s/scratch/wrap_libsn_ies_specman_exe.so
    #------------------------------------------------------------
    #
    # Compiling the following files:
    # ------------------------------
    # /vobs/wlip_zebra/verif/wl_phy/SPECMAN/E_USR/precompile.e
    #
    /sim1/zebra/wl_phy/wlip_zebra_eyalm/SNAPSHOTS/wl_phy_tb/wl_phy_tb.lnx8664.11.10.nc/specman.11.10.050-s/scratch/wrap_libsn_ies_specman_exe.so
    Welcome to Specman Elite(64) c_routine (11.10.050-s Build 320)  -  Linked on
    Thu Oct  4 17:11:08 2012

    Protected by U.S. Patents 6,141,630 ;6,182,258; 6,219,809; 6,347,388;
    6,487,704; 6,499,132; 6,502,232; 6,519,727; 6,530,054; 6,675,138; 6,684,359;
    6,687,662; 6,907,599; 6,918,076; 6,920,583; Other Patents Pending.

    Checking license ... OK
    Translating /vobs/wlip_zebra/verif/wl_phy/SPECMAN/E_USR/precompile.e ...
    read...parse...update...patch...h code...code...clean...save...
    Translation complete


    #------------------------------------------------------------
    # Compiling C modules using /apps/cds/incisiv/11.10.012/tools.lnx86/cdsgcc/gcc/bin/64bit/gcc
    #------------------------------------------------------------
    #------------------------------------------------------------
    # Compiling Specman main
    #------------------------------------------------------------
    #------------------------------------------------------------
    # Linking shared library 'libsn_precomp.so' using /apps/cds/incisiv/11.10.012/tools.lnx86/cdsgcc/gcc/bin/64bit/ld
    #------------------------------------------------------------
    # >>> Created /sim1/zebra/wl_phy/wlip_zebra_eyalm/SNAPSHOTS/wl_phy_tb/wl_phy_tb.lnx8664.11.10.nc/specman.11.10.050-s/scratch/precomp.ols
    # SNAPSHOTS/wl_phy_tb/wl_phy_tb.lnx8664.11.10.nc/specman.11.10.050-s/scratch/libsn_precomp.so is ready.


    Output for ncvlog is being redirected to /vobs/wlip_zebra/verif/wl_phy/SPECMAN/LOGS/ncvlog_wl_phy_tb.log
    ncvlog: *W,TOOMNV: more than one -VIEW option (only 'ncrun' used).
    file: /sim1/zebra/wl_phy/wlip_zebra_eyalm/SNAPSHOTS/wl_phy_tb/wl_phy_tb.lnx8664.11.10.nc/specman.11.10.050-s/runvstub.v
        module current.specman:ncrun
            errors: 0, warnings: 0
        module current.specman_wave:ncrun
            errors: 0, warnings: 0
        Total errors/warnings found outside modules and primitives:
            errors: 0, warnings: 1
    Output for ncelab is being redirected to /vobs/wlip_zebra/verif/wl_phy/SPECMAN/LOGS/ncelab_wl_phy_tb.log
    irun: *E,ELBERR: Error during elaboration (status 1), exiting.
    TOOL:    irun(64)    11.10-s053: Exiting on Oct 04, 2012 at 17:12:15 IST  (total: 00:01:03) 
     

     

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  • TAM1
    TAM1 over 12 years ago

    Apparently the -xlmode switch is passed from 'irun' to 'ncelab' telling the tool that it was invoked in single-step mode and to use the old 'verilog-xl' method of resolving modules. I had access to some really old software as far back as 2008 and every time I used 'irun' and "-binding" I got that warning message.

    You could override it using a Verilog configuration, I guess. But that's more complex than I can describe in a forum posting.

     

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