Outputting a synthesized file in reverse order

 Hi,

 I wanted to write the output of a synthesized verilog file in reverse order. Here is an example. If rtl compiler (RC) generates the following:

module .. (..) ;

// list of wires

...

// gate-level netlist (let's say there are only three gates)

 AND2_X1 (...);

OR2_X1 (...) ;

INV_X1 (...);

endmodule

What I would like to see is as follows:

module .. (..) ;

// list of wires

...

// gate-level netlist (netlist is reversed)

INV_X1 (...); 

OR2_X1 (...) ;

 AND2_X1 (...);

 endmodule

Is there a command in RC that reverses the order in which netlist is written. I want to do this because it was observed that inputs of upper gates are outputs of lower gates. I need to use this netlist in C++ code and there, with the orginial ordering, I would get incorrect output. I can ofcourse do some scripting but that's cumbersome. Is there a clean way in RC?

Thanks

Ankur