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Wanted to know the behaviour of RC on different SDC command

tanyacool

 This is something very unusual regarding the behaviour of RC on different SDC commands provided to it.

I had 2 sdc of the same design:

One sdc was which i had written it manually

Second one was the SDC generated by Spyglass tool.

The interesting thing to be noted here was that with the first SDC file, the tool was showing no error in the log while reading SDC command, but there was a error reported by the second SDC file in the logs.

The Error showed was like this:

Could not interpret SDC command. [SDC-202] [read_sdc] and that too on simple SDC commands.

create_clock

set_clock_uncertainty
set_case_analysis

 So in this case wanted to know the behavior of RC on the above SDC commands.

 

thanks 

tanyacool

  • Hi Tanyacool,

    There is no distinction between the Spyglass SDC and your hand created and the commands you mention should be fully supported provided the syntax is legal per SDC app. note

    The commands you mention are all supported in full throughout the flow so I would expect some issue in the syntax causing the errors but it is hard to tell without seeing the full log or the SDC. I suggest you share that with your local support or share with the forum if that is possible for you.

    hope this helps,

    gh-

  • hi grasshopper, 

    i just cross checked again with my designregarding the SDC written, the mistake was on my end as the memory.v was also being fed to Spyglass tool, so it was throughing the error, but the SDC which i was writting manually did not have the memory module so it was passing.

     

    Thanks for the clarification.

     Thanks 

    tanyacool

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