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what dose pulse width mean in timing report

small5

when I check timing report after synthesis, I got this: 

 

            Pin                             Type              Fanout Load Slew  Delay Arrival   

                                           (Domain)                  (fF) (ps)  (ps)    (ps)    

------------------------------------------------------------------------------------------------

(clock ifclk)                      launch                                               28500 F 

                                   latency                                      +3000   31500 F 

u_busif_sw

  rtc_sel_reg_enc_s_reg[3]/CZ                                                0          31500 F 

  rtc_sel_reg_enc_s_reg[3]/Q       RTCHLALCQ_F1_MP_PM_HVT(6)       2 13.8  382  +1649   33149 F     -- latch

  g170/B                                                                           +0   33149   

  g170/Y                           NOR2_B1_XSVT(6)                 2 13.2  163   +321   33470 R 

  g168/B1                                                                          +0   33470   

  g168/Y                           AOI13_D1P6_XSVT(6)              1  5.9  102   +141   33611 F 

  rtc_mdb_write_s_reg[15]/D   (b)  RTCHLALCQ_F1_PM_HVT(6)                          +0   33611 F     --latch

- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 

(clock ifclk)                      capture                                              56909 R 

                                   latency                                      +3000   59909 R 

                                   uncertainty                                   -500   59409 R 

                                   adjustments                                  -5182   54227   

                                   pulse width                                 -28409   25818   

                                   latch_borrow                                    +0   25818   

------------------------------------------------------------------------------------------------

Exception    : 'path_adjusts/from_ifclk_to_ifclk_setup_uncertainty_from_fall_to_rise' path adjust   -5182ps

Cost Group   : 'C2C' (path_group 'C2C_func')

Timing slack :   -7793ps (TIMING VIOLATION)

Start-point  : u_busif_sw/rtc_sel_reg_enc_s_reg[3]/CZ

End-point    : u_busif_sw/rtc_mdb_write_s_reg[15]/D

Mode         : func

this path is from latch to latch.  i don't know what dose the "pulse width" mean in this report. my RC version is: Version RC11.23 - v11.20-s024_1 

 who can explain this for me. thanks. 

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