Stats

  • Locked Locked
  • Replies 2
  • Subscribers 61
  • Views 15108
  • Members are here 0
This discussion has been locked.
You can no longer post new replies to this discussion. If you have a question you can start a new discussion

Reading Netlists with SEQGEN primitive

archive

I wonder if others have solutions for reading netlists containing "SEQGEN" generic registers into LEC? If I read an RTL design into "another synthesis tool" and write out the netlist before technology mapping, the registers are implemented with these generic flip-flops. Any tricks to deal with this? Is there a SEQGEN Verilog model available, for example? I know I could run mapping in the synthesis tool, but then you're not strictly verifying the pre-mapping netlist.


Originally posted in cdnusers.org by jbusco@nvidia.com
Parents

  • Hi

    I don't see SEQGEN defined in gtech.v. It's probably relatively easy to define that cell though, if you know the ports and the behaviour.

    Why do you want to read that netlist in though?

    Cheers,
    Chrystian


    Originally posted in cdnusers.org by croy
Reply

  • Hi

    I don't see SEQGEN defined in gtech.v. It's probably relatively easy to define that cell though, if you know the ports and the behaviour.

    Why do you want to read that netlist in though?

    Cheers,
    Chrystian


    Originally posted in cdnusers.org by croy
Children
No Data

Community Guidelines

The Cadence Design Communities support Cadence users and technologists interacting to exchange ideas, news, technical information, and best practices to solve problems and get the most from Cadence technology. The community is open to everyone, and to provide the most value, we require participants to follow our Community Guidelines that facilitate a quality exchange of ideas and information. By accessing, contributing, using or downloading any materials from the site, you agree to be bound by the full Community Guidelines.