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RTL Complier flow with clock gating and scan insertion

Terry2000

Hello, 

I've been struggling to scan insert and clock gate a small design, I believe I've been flowing the recommended flow:

1. If I clock gate by setting "set_attribute lp_insert_clock_gating true" then "connect_chains" in the flow any flops that have been clock gated are not in the scan chain. They appear to fail the dft check because of the clock gaing cell.

2. If I connect the chains first then clock gate using the command "clock_gating insert_in_netlist" this does all appear to work. However some of the scan flop are replaced with cells with an extra unnecessary enable added which is tied off with a 1'b1. 

3. To remove the 1'b1 I have "set_attribute avoid false {TIE0XM TIE1XM}" and "insert_tiehilo_cells -hi TIE1XM -lo TIE0XM".
Downstream I will be using EDI for the PnR, is it necessary to remove them here or will EDI cope (it appears to). I'm puzzled why the tool is adding this cell.

Any idea's why this is happening?

Parents

  •  Hello,

    Thanks for you reply, I did have that attribute set but I'd messed up on the syntax !

    I got it working last night with by using the test mode signal:

             set_attribute lp_clock_gating_test_signal scan_mode_in /designs/$ec::MODULE

    Then I tried your method today and this worked also:

             set_attribute lp_clock_gating_test_signal SE /designs/$ec::MODULE

    Thanks again for your help.

     

     

Reply

  •  Hello,

    Thanks for you reply, I did have that attribute set but I'd messed up on the syntax !

    I got it working last night with by using the test mode signal:

             set_attribute lp_clock_gating_test_signal scan_mode_in /designs/$ec::MODULE

    Then I tried your method today and this worked also:

             set_attribute lp_clock_gating_test_signal SE /designs/$ec::MODULE

    Thanks again for your help.

     

     

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