Stats

  • Locked Locked
  • Replies 2
  • Subscribers 61
  • Views 5744
  • Members are here 0
This discussion has been locked.
You can no longer post new replies to this discussion. If you have a question you can start a new discussion

TIP OF THE MONTH: How can I compare unreachable logic? Conformal LEC doesn't map nor compare it.

archive

How can I compare unreachable logic? Conformal LEC doesn't map nor compare it.

Important note: the settings discussed below make Conformal more picky than it really needs to be for regular EC. Do not employ them as default settings but, only when absolutely needed.

Unreachable logic is logic that doesn't affect the functionality of the design. Unreachable FF's and latches will appear in the mapping manager as yellow dots with a "U" inside. Since these compare points don't change the functionality they are not mapped nor compared by Conformal LEC. Typical unreachables: disabled logic (constraints), spare gates, or unconnected logic in the RTL (which synthesis will blow away).

There are times when you may want to compare unreachable logic. For example, if you are checking an IP block, have little knowledge of its functionality, and don't know if the unreachable logic should be unreachable. Also, it may also make it easier to debug the design with unreachables mapped and compared.

To preserve, map, and compare unreachable logic, do the following: When reading in your design, use the "-keep_unreach" option: 

read design rtl.v  -golden  -keep_unreach 
read design gate.v -revised -keep_unreach
After you've read in the designs but before mapping, issue the following command: 
set mapping method -unreach
The unreachable logic should now get mapped and compared.


Originally posted in cdnusers.org by darylk

  • Hello,

    As per your advice I tried to do the same but still i am having the same problem.

    I am trying to do a post syntheis(using netgen command after ngdbuild) vs. post PAR verification using Conformal tool. My problem is that I am getting unreachable points in "revised" design. I am using a hierarchical model (i am new to all these) and my .do file for conformal is as below


    set log file lec.top_mod_par.log -replace
    set naming rule "%s" -register -both

    set undriven signal 0 -both

    read design -f $XILINX/verilog/verplex/verilog.vc top_mod_ecn.v -golden -keep_unreach

    read design -f $XILINX/verilog/verplex/verilog.vc top_mod_par_ecn.v disp_clock_ecn.v -rev -keep_unreach

    set sys mode lec
    set mapping method -unreach
    report black box -detail
    add compare points -all
    compare

    top_mod_ecn.v : obtained using netgen command after ngdbuild on .edif netlist(from Synplify Pro)
    top_mod_par_ecn.v disp_clock_ecn.v : obtained using netgen after PAR (using ISE)

    a brief result from conformal is below :

    // Warning: Golden and Revised have different numbers of key points:
    // Golden key points = 80
    // Revised key points = 91
    // Mapping key points ...
    ================================================================================
    Mapped points: SYSTEM class
    --------------------------------------------------------------------------------
    Mapped points  PI    PO    DFF    BBOX    Total
    --------------------------------------------------------------------------------
    Golden              2       28    49       1          80
    --------------------------------------------------------------------------------
    Revised             2       28    49       1          80
    ================================================================================
    Unmapped points:
    ================================================================================
    Revised:
    --------------------------------------------------------------------------------
    Unmapped points BBOX Total
    --------------------------------------------------------------------------------
    Unreachable             11    11
    ================================================================================
    // Command: add compare points -all
    // 78 compared points added to compare list
    // Command: compare
    ================================================================================
    Compared points    PO    DFF    BBOX    Total
    --------------------------------------------------------------------------------
    Equivalent                28    49         1        78
    ================================================================================
    // Command: set mapping method -unreach
    // Command: report black box -detail
    SYSTEM (empty): X_DCM_ADV


    I will be very much thankful if someone could give a light on my problem.

    ciao,
    ali.


    Originally posted in cdnusers.org by alihusaini

  • Hello Ali,

    I don't think this module has any problem.  The result of the comparison for this module is equivalent.

    ==================================================
    Compared points    PO    DFF    BBOX    Total
    --------------------------------------------------------------------------------
    Equivalent                28    49         1        78
    =========================================
     
    To be able to map all the unreachable, the keypoints must be existing on both sides.  Just like default flow. In your case, the unreachable key points are only in the revised.  There are nothing to map with from the Golden.

    Hope this helps. 

    Regards,
    Jess


    Originally posted in cdnusers.org by jessican

Community Guidelines

The Cadence Design Communities support Cadence users and technologists interacting to exchange ideas, news, technical information, and best practices to solve problems and get the most from Cadence technology. The community is open to everyone, and to provide the most value, we require participants to follow our Community Guidelines that facilitate a quality exchange of ideas and information. By accessing, contributing, using or downloading any materials from the site, you agree to be bound by the full Community Guidelines.