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Disable Scan Shift Enable in Functional Mode

Terry2000

Hello,

I'm trying to disable shift enable in function mode.  

This is the VHDL code:
 i_scan_shift_enable <= '0' when scan_mode_in = '0' else scan_shift_enable;
   

So "scan_shift_enable" is driven from a pad and  "i_scan_shift_enable" drives the flops.

However I can't seem to keep net i_scan_shift_enable preserved and even if I did would it be a valid pin for the DFT tools to hookup to.

How is this generally done? Is it necessary to instantiate tech cell, preserve and hookup to the output pin?  

Parents
  • Hello,

    Many thanks for your reply, it was very helpful.

    So I created a small hierarchal block for the shift enable gate and used this command as your suggestion.

    define_dft shift_enable -name SE -active high -hookup_pin [find / -pin hlt5000_toplevel/u_scan_shift_gate/scan_shift_enable_gate] -hookup_polarity non_inverted [find / -port scan_shift_enable]

    I am using clock gating and use the following command to hook-up SE.

    set_attribute lp_clock_gating_test_signal SE /designs/ hlt5000_toplevel

    After using your suggested “define_dft shift_enable” command the design failed DFT rules for any flops with clock gating.

    I then change the clock gating hook-up to:

    set_attribute lp_clock_gating_test_signal scan_mode_in /designs/hlt5000_toplevel

    And this passed DFT rules and all looked good except I suffered a small drop off in faults coverage.

    Is it possible to use an internal shift enable signal clock gating control.  I tried various commands on the clock gating control (adding paths etc) without success.  

    Best Regards  
Reply
  • Hello,

    Many thanks for your reply, it was very helpful.

    So I created a small hierarchal block for the shift enable gate and used this command as your suggestion.

    define_dft shift_enable -name SE -active high -hookup_pin [find / -pin hlt5000_toplevel/u_scan_shift_gate/scan_shift_enable_gate] -hookup_polarity non_inverted [find / -port scan_shift_enable]

    I am using clock gating and use the following command to hook-up SE.

    set_attribute lp_clock_gating_test_signal SE /designs/ hlt5000_toplevel

    After using your suggested “define_dft shift_enable” command the design failed DFT rules for any flops with clock gating.

    I then change the clock gating hook-up to:

    set_attribute lp_clock_gating_test_signal scan_mode_in /designs/hlt5000_toplevel

    And this passed DFT rules and all looked good except I suffered a small drop off in faults coverage.

    Is it possible to use an internal shift enable signal clock gating control.  I tried various commands on the clock gating control (adding paths etc) without success.  

    Best Regards  
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