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Error saying "Direction of module port... is not defined" bit blasted verilog netlist

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Hi,

I'm getting the following error during formal verification (LEC) RTL to Netlist.
The netlist is verilog by nature and the port at which the error occurs has "\" before the name.
The port is a multi-bit vector. 
For example: \POINTER_DIFFOUT[0], \POINTER_DIFFOUT[1], \POINTER_DIFFOUT[2]...

The Error message says "Direction of module port \POINTER_DIFFOUT[0] in Module is not defined.

From what I understand, the port \POINTER_DIFFOUT[*] is bit blasted and does not have a specific vector direction.

Is there a way to specify the direction to LEC such that this error is resolved.

I'd appreciate any help.

Thanks and Regards,
Vardhan.


Originally posted in cdnusers.org by ljv_vardhan

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