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Query Post Synthesis vs. Post PAR verification using Conformal

archive
archive over 17 years ago

Hello all,

I am trying to do a post syntheis(using netgen command after ngdbuild) vs. post PAR verification using Conformal tool. My problem is that I am getting unreachable points in "revised" design. I am using a hierarchical model (i am new to all these) and my .do file for conformal is as below


set log file lec.top_mod_par.log -replace
set naming rule "%s" -register -both

set undriven signal 0 -both

read design -f $XILINX/verilog/verplex/verilog.vc top_mod_ecn.v -golden -keep_unreach

read design -f $XILINX/verilog/verplex/verilog.vc top_mod_par_ecn.v disp_clock_ecn.v -rev -keep_unreach

set sys mode lec
set mapping method -unreach
report black box -detail
add compare points -all
compare

top_mod_ecn.v : obtained using netgen command after ngdbuild on .edif netlist(from Synplify Pro)
top_mod_par_ecn.v disp_clock_ecn.v : obtained using netgen after PAR (using ISE)

a brief result from conformal is below :

// Warning: Golden and Revised have different numbers of key points:
// Golden key points = 80
// Revised key points = 91
// Mapping key points ...
================================================================================
Mapped points: SYSTEM class
--------------------------------------------------------------------------------
Mapped points  PI    PO    DFF    BBOX    Total
--------------------------------------------------------------------------------
Golden              2       28    49       1          80
--------------------------------------------------------------------------------
Revised             2       28    49       1          80
================================================================================
Unmapped points:
================================================================================
Revised:
--------------------------------------------------------------------------------
Unmapped points BBOX Total
--------------------------------------------------------------------------------
Unreachable             11    11
================================================================================
// Command: add compare points -all
// 78 compared points added to compare list
// Command: compare
================================================================================
Compared points    PO    DFF    BBOX    Total
--------------------------------------------------------------------------------
Equivalent                28    49         1        78
================================================================================
// Command: set mapping method -unreach
// Command: report black box -detail
SYSTEM (empty): X_DCM_ADV


I will be very much thankful if someone could give a light on my problem.

ciao,
ali.


Originally posted in cdnusers.org by alihusaini
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  • archive
    archive over 17 years ago

    Hi Ali

    Unreachables are a problem only if unexpected. In the log you're showing the verification passes (you would get an exit code of '0').

    I would remove '-keep_unreach' and 'set mapping method -unreach' from you dofile to help cut down on the warnings.

    I don't like using 'set undriven signal 0 -both'. See the 'tip of the month' from February 28 to know why.

    You can use 'report verification' and 'set exit code -verbose' to get a clear picture of the result. You can even customize the messaging, like this:

    tclmode
    if {[get_exit_code] == 0} {
    puts "Verification passed. Awesome"
    } else {
    puts "Problem with run. Darn"
    }
    vpxmode

    Chrystian


    Originally posted in cdnusers.org by croy
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  • archive
    archive over 17 years ago

    Hi Chrystian,

    I am still having the problem. I just wish to flag the black box so as to go away with verification and that is why "keep_unreach" and "set mapping method -unrecah" is used.I am not finding any solution to do so. neither in gui nor though command writng. I just wish to tell the tool that my design have such module and it shoulf flag/ignore them and continue with verification.

    Thanks,
    Ali.


    Originally posted in cdnusers.org by alihusaini
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    • Vote Up 0 Vote Down
    • Cancel
  • archive
    archive over 17 years ago

    Hi Chrystian,

    I am still having the problem. I just wish to flag the black box so as to go away with verification and that is why "keep_unreach" and "set mapping method -unrecah" is used.I am not finding any solution to do so. neither in gui nor though command writng. I just wish to tell the tool that my design have such module and it shoulf flag/ignore them and continue with verification.

    Thanks,
    Ali.


    Originally posted in cdnusers.org by alihusaini
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  • archive
    archive over 17 years ago

    Hi Ali

    I don't understand the issue here. The tool is ignoring it and continuing, and the end result is equivalent (you'll get an exit code of '0').

    Please file an SR through http://sourcelink.cadence.com if you're still unclear.

    Cheers,
    Chrystian


    Originally posted in cdnusers.org by croy
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