Stats

  • Locked Locked
  • Replies 1
  • Subscribers 61
  • Views 13635
  • Members are here 0
This discussion has been locked.
You can no longer post new replies to this discussion. If you have a question you can start a new discussion

RTL vs. gate netlist verification mapping problem

archive

hello people,

I am doing RTL vs. gate netlist verification. I used "vif2conformal" tcl script in synplify pro to convert the verification file (.vif) obtained from synplify to conformal readable files( it generates many others .vtc, .vmc, etc.).
My problem is that the main dofile for conformal (i.e. .vtc file) calls anothers generated dofile file (.vmc mapping file). This .vmc file consist of mainly memories and some DFF (nearly 242735 lines) and i wish to bypass this map file by first black boxing the m/m and secondly "renaming" the DFFs.
The black boxing is done but i am not able to use the "add renaming rule" comand. I am attaching the extract from .vmc file in mail which i need to rename for fast processing.

Hope (and wish) that  if any of you could take some precious time out and help me doing so.

Thanks and regards,
ali.

wish that sometime i too reach a stage to help others :+)


Originally posted in cdnusers.org by alihusaini
Parents Reply Children
No Data

Community Guidelines

The Cadence Design Communities support Cadence users and technologists interacting to exchange ideas, news, technical information, and best practices to solve problems and get the most from Cadence technology. The community is open to everyone, and to provide the most value, we require participants to follow our Community Guidelines that facilitate a quality exchange of ideas and information. By accessing, contributing, using or downloading any materials from the site, you agree to be bound by the full Community Guidelines.