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verilog .v lib vs synopsis .lib

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Hi

What kind of lib do you recommend to use verilog stdcell.v vs synopsys *.lib.
When verilog lib is used, we have gated clock convertion problem.
When .lib used, we have some of cells being black boxed.

Best Regards
Joseph


Originally posted in cdnusers.org by jowu

  • Hi Joseph

    Verilog is typically preferred since that's your golden library.

    I would run EC, comparing Verilog and Liberty. Search for "library qualification" on sourcelink. It's pretty easy to do.

    You can also mix-and-match:

    read library -verilog *.v
    read library -liberty -append *.lib

    Chrystian


    Originally posted in cdnusers.org by croy

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