Stats

  • Locked Locked
  • Replies 1
  • Subscribers 61
  • Views 12910
  • Members are here 0
This discussion has been locked.
You can no longer post new replies to this discussion. If you have a question you can start a new discussion

Non-equivalences due to different device.

archive

Hi,

I have performed Equivalence check (Using Encounter CONFORMAL (R)  Version 07.10-s140 )  between two verilog netlists generated by two different Quartus Versions targeting two different ALTERA devices.
 Devices Used :
  • Stratix ( EP1S30F780I6) used for Revised netlist.
  • Stratix II ( EP2S30F484I4) used for Golden netlist.
 Quartus Versions Used:
* Version 5.1 Build 176 10/26/2005 Service Pack 0.15 SJ ( For Stratix, Revised Netlist ).
* Version 6.1 Build 201 11/27/2006 SJ Full Version ( For STRATIX II, Golden Netlist)
Here netlist refers to Verilog Formal verification O/P Netlist  generated by Quartus tool on both sides.
There were non-equivalences generated due to architecture differences of different devices. Please note that there were  no changes in RTL's used, except the modification done on soft macro's with respect to device.

Observation of Errors:
STRATIXII device drives clock output of the PLL to CLOCK CONTROL BUFFER which in turn drives clock output into design blocks. Whereas STRATIX device  doesn’t use CLOCK CONTROL Buffer and clock output of PLL is directly driven to design blocks.

I understood that there will be differences; however i would like to know if there are any Conformal Settings or Commands related to these devices to resolve non equivalences.
Please find the script attached that was used for performing LEC Verification. Extract of Non-equivalence error report is attached as well .

Kindly give your suggestions and comments and feel free to ask me if you require further inputs.
Thanks in advance,
Warm regards,
Dina.


Originally posted in cdnusers.org by caddina
Script and Error report.zip
Parents

  • Hi Dina

    I can't tell from the piece of log attached what's going on. Please open an SR through http://sourcelink.cadence.com and attach the full log.

    Is clock control buffer a black-box? If it is then that would be a problem for EC. You need to have a correct model for it or, if you're absolutely certain that the 2 nets are the same then you could use 'add primary input' on them to put as PI's. All that would be left is to do 'add mapped point'.

    BTW You would probably have an easier time doing 2 RTL-gate runs than 1 gate-gate. This was discussed in the tip of the month posted on 6/13/2007 on this forum.

    Chrystian


    Originally posted in cdnusers.org by croy
Reply

  • Hi Dina

    I can't tell from the piece of log attached what's going on. Please open an SR through http://sourcelink.cadence.com and attach the full log.

    Is clock control buffer a black-box? If it is then that would be a problem for EC. You need to have a correct model for it or, if you're absolutely certain that the 2 nets are the same then you could use 'add primary input' on them to put as PI's. All that would be left is to do 'add mapped point'.

    BTW You would probably have an easier time doing 2 RTL-gate runs than 1 gate-gate. This was discussed in the tip of the month posted on 6/13/2007 on this forum.

    Chrystian


    Originally posted in cdnusers.org by croy
Children
No Data

Community Guidelines

The Cadence Design Communities support Cadence users and technologists interacting to exchange ideas, news, technical information, and best practices to solve problems and get the most from Cadence technology. The community is open to everyone, and to provide the most value, we require participants to follow our Community Guidelines that facilitate a quality exchange of ideas and information. By accessing, contributing, using or downloading any materials from the site, you agree to be bound by the full Community Guidelines.