LEC Hier-compare when sub modules have extra port in Revised Design!!

Hi, We have a question regarding LEC. We have asked our syntesis tool to introduce clock gating cells while preserving limited hierarchy(ie. our chip has 10 modules and each module has 100 submodules. We are preserving hierarchy of our 10 modules while flattening them inside).(we want to run Conformal on each of the 10 modules separately). Synthesis tool has mostly placed clock gating cells inside the module hierarchy. For some modules, it has placed a clock gating cell outside the module. Output of these clock gating cells are going inside the modules i.e. an extra clock port is added in revised design. How to handle such a scenario. 'ADD ECO PIN' is not enough because we need to tell Conformal that extra port is the output of clock gating cell. - Thanks