The same design can be synthesized by Synopsys (syn-2010.03-SP3). No error happens. When I use Cadence RTL compiler, one error happens. The error information is listed as below.

Library:  CORE65GPLVT_nom_1.10V_25C.lib
             CLOCK65GPLVT_nom_1.10V_25C.lib

Error   : Unable to map design without a suitable latch. [MAP-3] [synthesize]
          : Instance 'U1/full_nx_reg' requires a simple latch.
          : Check the libraries for necessary latch cell. The cell could be marked unusable.
            Synthesis failed.

Code: 

   WHEN "10" =>
             IF (full_nx /= '1') THEN
                  wptr_nx <= wptr_reg;
                empty_nx <= '0';    
                    wen_nx <= '1';
                     ren_nx <= '0';
                   IF (wen_nx = '1') THEN
                      wptr_nx <= wptr_suc;    
                   END IF;
            ELSE
               wen_nx <= '0';
               ren_nx <= '0';
            END IF;

            IF (wptr_suc = rptr_reg) THEN
               full_nx <= '1';
               wen_nx  <= '0';
            ELSE
              full_nx <= '0';
            END IF;

Could you please give me some suggestions? I 'd appreciate any help I can get.

Thank you very much.

Li