Asynchronous FIFO design

Thanks for the response. The book is goond for understanding the aspects of asynchronous design but the FIFO presented in the book is somewhat peculiar and uses shift register and not a generic fifo. However i came across a paper by cliff cummings on FIFO design which was very basic and well explained.

As it seems that paper is quite famous  i would like to ask some question regarding the design in the paper or Async FIFO design in general as the design is very basic

1) In the design 2 FF synchronizer is used for both read pointer and write pointer . won't it depend on clock domain crossing?as from slow to fast CDC using a 2 FF synchronizer is fine but from fast to slow CDC the 2 FF design may not work. so should we be using different synchronizer at fast to slow CDC and slow to fast CDC.

2)  Full and empty check :  He has written that the updation would be immediate but i think differently,
    assuming a situation where W_clk is faster than R_clk, two cases would arrive
     a) when w_clk is marginally faster than the R_clk then the Rpointer value in the write pointer domain would arrive 2 rclk cycles later
          and hence FIFO FULL would be asserted at FIFO depth -2.
    
     b) when W_clk is much faster than the R_clk then the Rpointer value in the write pointer domain would arrive 2 rclk cycles later
          and hence FIFO FULL would be asserted at FIFO depth - (some value).
        in both the case the FIFO FULL detection is not immediate. and same goes for empty check condition too (applying different set of conditions).

 plz enlighten me on the issue.

regards,

abhinavpr

Thanks for the response. The book is goond for understanding the aspects of asynchronous design but the FIFO presented in the book is somewhat peculiar and uses shift register and not a generic fifo. However i came across a paper by cliff cummings on FIFO design which was very basic and well explained.

As it seems that paper is quite famous  i would like to ask some question regarding the design in the paper or Async FIFO design in general as the design is very basic

1) In the design 2 FF synchronizer is used for both read pointer and write pointer . won't it depend on clock domain crossing?as from slow to fast CDC using a 2 FF synchronizer is fine but from fast to slow CDC the 2 FF design may not work. so should we be using different synchronizer at fast to slow CDC and slow to fast CDC.

2)  Full and empty check :  He has written that the updation would be immediate but i think differently,
    assuming a situation where W_clk is faster than R_clk, two cases would arrive
     a) when w_clk is marginally faster than the R_clk then the Rpointer value in the write pointer domain would arrive 2 rclk cycles later
          and hence FIFO FULL would be asserted at FIFO depth -2.
    
     b) when W_clk is much faster than the R_clk then the Rpointer value in the write pointer domain would arrive 2 rclk cycles later
          and hence FIFO FULL would be asserted at FIFO depth - (some value).
        in both the case the FIFO FULL detection is not immediate. and same goes for empty check condition too (applying different set of conditions).

 plz enlighten me on the issue.

regards,

abhinavpr