How to avoid unwanted removal of logic during synthesis

Hi All,

I am synthesizing a processor design with RTL compiler. The synthesized netlist works fine and contains all necessary logic when I set a loose clock constraint (5000ps). But when I synthesized the same files with a tighter clock constraint (1800- 3000ps) the RTL compiler meets the constraint but randomly removes some of the registers(i.e  Register file of the processor) in the synthesized netlist, which are required for proper operation of the design and are not some undriven or extra logic. Is there a way to instruct RTL compiler what not to remove?

The attributes I am using are as follows:

set_attribute hdl_track_filename_row_col true /

set_attribute hdl_undriven_signal_value 0

set_attribute hdl_infer_unresolved_from_logic_abstract false /

set_attribute information_level 2

Thanks.