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power differences after post-syn using VCD

leez2006

Hi,

I want to get a quick look at the power consumption of one block.

--use RTL Compiler generate netlist(after syn) and sdf

--run gate sim with or without sdf annotated, get VCD

--use netlist and VCD in ETS, get power consumption

I found the power consumption get form VCD without sdf annotated is much greater than with sdf annotated.

This makes me confuse. I think the power with sdf annotated should be bigger. Can anyone help to explain this?

I found there is only one difference with the log (the value changes got from vcd).

without sdf annotated:

With this vcd command,  12005021 value changes and 1e-06 second
simulation time were counted for power consumption calculation.

  Filename (activity)                    :
../in/ad9651_datapath_top_gate.vcd
  Names in file that matched to design   : 234754/352833
  Annotation coverage for this file      : 54305/54305 = 100%

Activity annotation summary:
        Primary Inputs : 89/89 = 100%
          Flop outputs : 8172/8172 = 100%
  Memory/Macro outputs : 0/0 = 0%
      Tristate outputs : 0/0 = 0%
            Total Nets : 54305/54305 = 100%

with sdf annotated:

With this vcd command,  6867391 value changes and 1e-06 second
simulation time were counted for power consumption calculation.

  Filename (activity)                    :
../in/ad9651_datapath_top_gate.vcd
  Names in file that matched to design   : 234754/352833
  Annotation coverage for this file      : 54305/54305 = 100%


Activity annotation summary:
        Primary Inputs : 89/89 = 100%
          Flop outputs : 8172/8172 = 100%
  Memory/Macro outputs : 0/0 = 0%
      Tristate outputs : 0/0 = 0%
            Total Nets : 54305/54305 = 100%

Parents

  • Hey, gh

     Thanks for your reply.

    What I want to compare is

    netlist(after syn) + gate_VCD(without sdf annotation) VS netlist(after syn) + gate_VCD(with sdf annotation).

    The power analysis tool is ETS for both. The sdf is generated after syn. The netlist is the same.

    In your reply you said you noticed the annotation is different yet I used the same netlist, do you mean "12005021 value changes" and "6867391 value changes "? That's what confused me. I don't know how the ETS get value changes from VCD, but I think the VCD with sdf annotation shoud have more transitions(the combitional cells would toggle more for it's inputs have different delay).

    leez

Reply

  • Hey, gh

     Thanks for your reply.

    What I want to compare is

    netlist(after syn) + gate_VCD(without sdf annotation) VS netlist(after syn) + gate_VCD(with sdf annotation).

    The power analysis tool is ETS for both. The sdf is generated after syn. The netlist is the same.

    In your reply you said you noticed the annotation is different yet I used the same netlist, do you mean "12005021 value changes" and "6867391 value changes "? That's what confused me. I don't know how the ETS get value changes from VCD, but I think the VCD with sdf annotation shoud have more transitions(the combitional cells would toggle more for it's inputs have different delay).

    leez

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