The error of Synthesis

Hi friends,

I  synthesize a very simple veirlog code but I got an following error when I did "synthesize -to_mapped". There is nothing between the single quotes. How can I find what and where the error is? I will list my code and tcl file. BTW, I used RTL Compiler. Thanks.

Error   : A required object parameter could not be found. [TUI-61] [get_attribute]

        : An object named '' could not be found.

        : Check to make sure that the object exists and is of the correct type.  The 'what_is' command can be used to determine the type of an object.

Usage: get_attribute <string> [<object>+]

    <string>:

        attribute name 

    [<object>+]:

        object of interest (must be unique) 

 -------------verilog code------------

module test1

  (

    clk,

    rst,

    x_in,

    y_in,

    x_out

  );

input clk,rst;  

input [15:0] x_in, y_in;

output [15:0] x_out;

reg [15:0] x_out;

wire flag;

assign flag = x_in[15];

always @(posedge clk or negedge rst)

if (~rst)

x_out<='d0;

else

begin

if (flag)

x_out<=x_in+y_in;

else

x_out<=x_in-y_in;

end

endmodule 

----------------------------tcl-----------------------------------------------------------------------

set_attribute lib_search_path {/users/bh/class/CPE411/STD/Synopsys}

set_attribute library {/users/bh/class/CPE411/STD/Synopsys/smic13_ff_1p32v_0c.lib}

read_hdl -v2001 {/users/bh/class/CPE411/syn1/source/test1.v}

set target_technology smic13_ff_1p32v_0c

elaborate

check_design

read_sdc -stop_on_errors /users/bh8/class/CPE411/syn1/script/timing.sdc

synthesize -to_mapped