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Force RTL compiler not to optimize certain part of the design

rexnyu

Hi,

I have a verilog design which has an input A which is 128-bit. I would like to use assign statement to let A equals to a fix value.

But I don't want RTL compiler to optimize the logic associated with A, because I will give different values for A later in the spice level simulation. 

Is there any synthesis constraints that can achieve this purpose? 

 

Thank you very much! 

 

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