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delay between 2 signals

vvgulyaev
Hello, i am beginner rtl compiler user. I have a question about synthesis with rtl compiler.

For example, i have 2 signals sig1 and sig2. In verilog code:

[CODE]assign #10 sig2=sig1;[/CODE]
In synthesis I want to insert delay buffer between sig2 and sig1. Library which I want to use is contain delay buffer cells for different time delays. But i don't know which tcl command for rtl compiler inserts delay buffer between 2 signals.

  • Verilog delay statement are not synthesizable and synthesis tools simply ignore them. Multiple ways swap a buffer for a delay cell so please check with your local AE.There is no verilog statement to ensure a buffer or delay cell is inserted short of hand-instantiating the delay cells

     gh-

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