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how to find power of a design based on inputs given to the design using cadence

samhitha nr
I am using clock gating in my design. When we use clock gating particular part of design will be dynamically off based on the requirement. Consider if there are two blocks (block1 and block2) in a design. For input1, only block1 will be switched on and block2 will be in OFF state. For next input i.e input2, only block2 will be in ON state and block1 will be in OFF state. So for different inputs different blocks will be in off or on state. Anyone please let me know how to calculate power for this kind of designs when the hardware used changes for different inputs. It would be very kind enough if you could reply to my query.. Thank you
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  •  Hi Samhitha,

    RC should take care of this but it is important the toggle activity feeding you XOR or other gating logic be accurate or else the propagation of it will certainly be inaccurate. You can do a quick experiment and check the activity of signals feeding XOR to be 0 and review the impact of it. 

     You can also query the value of attributes

     lp_asserted_toggle_rate (net)
      lp_asserted_toggle_rate (pin)
      lp_asserted_toggle_rate (port)
      lp_asserted_toggle_rate (subport)
      lp_computed_toggle_rate (constant)
      lp_computed_toggle_rate (net)
      lp_computed_toggle_rate (pin)
      lp_computed_toggle_rate (port)
      lp_computed_toggle_rate (subport)
      lp_default_toggle_percentage (clock)
      lp_default_toggle_percentage (design)
      lp_default_toggle_rate (design)
      lp_default_toggle_rate (instance)
      lp_default_toggle_rate (pin)
      lp_default_toggle_rate (port)
      lp_default_toggle_rate (root)

    as appropriate to determine what RC is doing during computation.

    Finally,  RC can also use lp_pso_aware_estimation attribute when blocks are shutoff through power rails in addition to clocks

    hope it helps,

    gh-

     

Reply

  •  Hi Samhitha,

    RC should take care of this but it is important the toggle activity feeding you XOR or other gating logic be accurate or else the propagation of it will certainly be inaccurate. You can do a quick experiment and check the activity of signals feeding XOR to be 0 and review the impact of it. 

     You can also query the value of attributes

     lp_asserted_toggle_rate (net)
      lp_asserted_toggle_rate (pin)
      lp_asserted_toggle_rate (port)
      lp_asserted_toggle_rate (subport)
      lp_computed_toggle_rate (constant)
      lp_computed_toggle_rate (net)
      lp_computed_toggle_rate (pin)
      lp_computed_toggle_rate (port)
      lp_computed_toggle_rate (subport)
      lp_default_toggle_percentage (clock)
      lp_default_toggle_percentage (design)
      lp_default_toggle_rate (design)
      lp_default_toggle_rate (instance)
      lp_default_toggle_rate (pin)
      lp_default_toggle_rate (port)
      lp_default_toggle_rate (root)

    as appropriate to determine what RC is doing during computation.

    Finally,  RC can also use lp_pso_aware_estimation attribute when blocks are shutoff through power rails in addition to clocks

    hope it helps,

    gh-

     

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