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clock gating in RC

doydodo

Hello.

What is the right way to insert clock gating in RC script?

How should i translate the following instructions form DC for RC ?

(DC) --> 

set_clock_gating_style -sequential_cell latch \

  -negative_edge_logic $CELL_NAME \

  -positive_edge_logic $CELL_NAME \

  -max_fanout 16 \

  -minimum_bitwidth 4 \

  -control_point before \

  -control_signal scan_enable

---------------------------------------------------------------------------------------------------------

(RC) -->

define_dft shift_enable -name scan_enable -active high $CELL_NAME1

define_dft shift_enable -name scan_enable -active low $CELL_NAME2

set_attr lp_insert_clock_gating true

set_attr lp_clock_gating_min_flops 4 [find/design -design $DESIGN]

set_attr lp_clock_gating_style latch [find/design -design $DESIGN]

set_attr lp_clock_gating_control_point precontrol [find/designs -design $DESIGN]

set_attr lp_clock_gating_test_signal scan_enable $DESIGN

 ---------------------------------------------------------------------------------------------------------

 Is it enough or there is something else needed?

 

 

  •  That looks right.  If you want to limit the fanout of the clock_gater to 16, then you will also want to add the lp_clock_gating_max_flops attribute, and set it to 16.  However, I think it is better to let the PnR tool clone the clock gaters, if necessary, to meet timing to the enable signal.

    Also, be sure you set the lp_insert_clock_gating attribute to true BEFORE you read and elaborate your RTL.

     

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